Embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a nonvolatile memory device and a method of manufacturing the same.
Technology for semiconductor devices is focused on an increase in a degree of integration. In order to increase the degree of integration of semiconductor devices, schemes for reducing the size of memory cells arranged in a 2-D way have been developed. But, a reduction in the size of the memory cells arranged in a 2-D way is limited. In order to overcome the limit, a 3-D semiconductor device in which memory cells are arranged in a 3-D way over a substrate has been proposed. The 3-D semiconductor device may efficiently utilize the area of the substrate and increase the degree of integration as compared with the case where the memory cells are arranged in a 2-D way.
A conventional 3-D structured memory device includes a plurality of gate lines stacked over a substrate. An interlayer insulating layer is interposed between adjacent the gate lines, thus insulating the gate lines from each other. A contact plug is coupled to each of the gate lines. To this end, the sides of the gate lines are stepwise patterned so that the contact regions of the gate lines to be coupled to the contact plugs are exposed.
FIGS. 1A to 1E are cross-sectional views illustrating a known method of manufacturing a conventional 3-D nonvolatile memory device. For simplicity, FIGS. 1A to 1E illustrate only the contact regions of the 3-D nonvolatile memory device.
Referring to FIG. 1A, a stack structure is formed by alternately stacking a plurality of interlayer insulating layers 10A to 10I and a plurality of conductive layers 20A to 20H over a substrate (not shown). Next, although not shown, processes of forming memory cells arranged in the form of a 3-D structure in memory cell regions are performed.
A mask pattern 30 for forming contact regions is formed on the interlayer insulating layers 10A to 10I and the conductive layers 20A to 20H. The mask pattern 30 may be a photoresist pattern formed by depositing a photoresist layer on the interlayer insulating layers 10A to 10I and the conductive layers 20A to 20H and patterning the photoresist layer using exposure and development processes.
Referring to FIG. 1B, the interlayer insulating layer 10I, which is the uppermost layer, and the conductive layer 20H, which is the uppermost layer, are etched using the mask pattern 30 as an etch barrier. Thus, a step {circle around (1)} is formed in the stack structure. It is noted that the step numbers refer to a position of a step in the stacked structure and not to an order in which the steps were formed. For example, step {circle around (1)} refers to the lowest existing step of the stacked structure, while step {circle around (2)} will refer to the next higher existing step. Next, a width of the mask pattern 30 is reduced by a width of a contact region by etching the mask pattern 30. Here, not only the width of the mask pattern 30, but also a thickness of the mask pattern 30 is reduced.
Referring to FIG. 1C, the interlayer insulating layer 10I and the conductive layer 20H are etched using the reduced mask pattern 30 as an etch barrier. The interlayer insulating layer 10I and the conductive layer 20H are again etched, thereby forming step {circle around (2)}. The insulating layer 10H and the conductive layer 20G, which underlie the interlayer insulating layer 10I and the conductive layer 20H, are etched, thereby forming step {circle around (1)}, in the stack structure. Next, the width of the mask pattern 30 is reduced by the width of a contact region by etching the mask pattern 30. Here, not only the width of the mask pattern 30, but also the thickness of the mask pattern 30 is reduced.
Referring to FIG. 1D, after reducing the width of the mask pattern 30 as described above, a series of processes of etching the interlayer insulating layer 10I and the conductive layer 20H, using the reduced mask pattern 30 as an etch barrier, are repeatedly performed until the conductive layer 20A, which is the lowermost layer, is etched. As a result, the stack structure is stepwise patterned from the conductive layer 20H to the conductive layer 20A, and the same number of steps as the number of conductive layers 20A to 20H is formed in the stack structure.
The case where the conductive layers 20A to 20H of eight layers are stacked is illustrated, for example. Accordingly, the first to eighth steps {circle around (1)} to {circle around (8)} may be formed.
The sides of the conductive layers 20A to 20H, which have been stepwise patterned, are defined as contact regions.
Referring to FIG. 1E, after removing the mask pattern 30, residual substances are removed through a cleaning process. Next, an insulating layer 40 is formed over the entire structure that has been stepwise patterned. A surface of the insulating layer 40 is polished. Next, contact holes, through which the respective contact regions of the conductive layers 20A to 20H, are exposed are formed. The contact holes are filled with a conductive layer, thereby forming a plurality of contact plugs 50A to 50H each coupled to a respective one the conductive layers 20A to 20H.
Conventionally, the thickness of the mask pattern 30 that is first formed must be thick enough to withstand the etch process of the mask pattern 30 that is repeatedly performed. For this reason, the thickness of the mask pattern 30 must be increased in proportion to the number of the conductive layers 20A to 20H that form the stack structure. As described above, the mask pattern 30 may be formed by performing the exposure and development processes on the photoresist layer. Accordingly, in order to increase the thickness of the mask pattern 30, the deposition thickness of the photoresist layer must be increased. If the thickness of the photoresist layer increases, there is a problem in that the time taken for the exposure process is increased. Furthermore, there are problems in that the number of processes of reducing the mask pattern 30 and the number of processes of etching the interlayer insulating layer 10I and the conductive layer 20H are increased according to the number of the conductive layers 20A to 20H that form the stack structure.